The present invention relates to a semiconductor device, and more specifically to a bipolar memory which has a high .alpha.-particle immunity and which is to be fabricated with a high integration density.
In the conventional bipolar memory as disclosed by JP-A-61-104655, all of Schottky barrier diodes SBD1 and SBD2, high resistive polycrystalline silicon layer, high resistive impurity-doped layer, and transistors TR1 and TR2 are arranged in a plane to form a flip-flop type of static bipolar memory cell circuit as shown in FIG. 2. However, the plane-like arrangement of constituent elements of the memory has a problem that an area required for the memory cell cannot be made small, thereby rendering high integration difficult.
U.S. Pat. No. 4,636,833 has proposed a bipolar memory in which the required area is reduced by superimposing an MOS capacitor on a Schottky barrier diode. In order to further improve the integration density of the bipolar memory, it is desired to further reduce the required area.
A semiconductor memory is subjected to an hindrance in that an erroneous storage may result from the presence of external .alpha. particles. This hindrance is generally called a soft error. Since the soft error increases as the integration density of the memory becomes higher, the prevention of the soft error is a very important problem for a semiconductor memory having a high integration density.